The invention relates to a non-volatile semiconductor memory device having a metal-insulating-semiconductor gate structure and a method for fabricating the same. Metal insulator semiconductor devices have been known in the art as a non-volatile semiconductor memory element and may be divided into two different types, one of which is a floating gate memory transistor and another one is a metal-nitride-oxide-semiconductor memory transistor. At this time, the floating gate memory transistor appears to be more widely used than the metal-nitride-oxide-semiconductor memory transistor. The floating gate transistor has dual gate electrodes wherein one is a floating gate completely surrounded by an insulator to be kept in an electrically floating state and provided over a channel region through the insulator and another is a control gate provided over the floating gate through the insulator. The control gate is applied with a positive voltage signal to apply an electric field between the control gate and the channel region so that hot electrons are caused on a channel region of the transistor. This may cause Fowler-Nordheim tunneling of the hot electrons from the channel region through the insulator into the floating gate thereby a write operation of informational signals is then achieved. An erasure operation may be achieved either by thermal means or by ultra violet irradiation to cause discharge of the informational electrons from the floating gate and then the electrons flow into the channel or source regions. The insulator between the channel region and the floating gate has such a large thickness as to cause Fowler-Nordheim tunneling, for example, at least more than 50 angstroms. Such large thickness of the insulator may also allow that the electrons once injected into the floating gate incline to be accumulated within the floating gate for a long time, for example, 1.times.10.sup.5 hours, provided that no electric field is applied across the floating gate during that term. The write state where electrons are accumulated in the floating gate may represent "1" in binary signals, while the erasure state where no or almost no electron remains in the floating gate may represent "0" in binary signals.
It is, however, hard to achieve a complete erasing operation due to a difficulty in exact emission or discharge of all electrons from the floating gate either by thermal means or by ultra violet irradiation. It is a factual matter that the majority of the electrons may be emitted from the floating gate by receiving either thermal means or ultra violet irradiation, while the minority of the electrons inclines to remain in the floating gate. In a subsequent write operation, electrons as another informational signals are further injected by the Fowler-Nordheim tunneling into the floating gate so that a total amount of the electrons in the floating gate is increased by the amount of the electrons having still remained therein after the previous erasing operation. After a subsequent erasing operation, a larger amount of electrons inclines to remain in the floating gate as compared to that after the previous erasing operation. This means that repeat of the sets of the write and erasing operations results in an increase of the amount of the electrons remaining in the floating gate after the erasing operation. As the amount of the electrons existing in the floating gate after the erase operation is gradually increased through repeating the above write and erase operations and may, thereafter, come over a critical amount at which the memory device comes unable to recognize the state "0" in the binary signals. As a result, a possible number of time in repeat of the write and erasing operations is necessarily limited. The maximum number of time in repeating the write and erase operations is in fact insufficient to the required number of time therefor. As the increase of the memory capacity is being now required, a much larger number of time, for example, 10.sup.5 of the sets of the write and erase operations are required.
As the requirements for increase of the memory capacity have been on the increase, importance in the requirement for increase of a possible number of time of the sets of the write and erasing operations is now on the great increase.
Under the above circumstances, the metal-nitride-oxide-semiconductor memory device comes now receiving a greater deal of attention as an attractive memory device due to its capability of a large number of time in repeat of the sets of the write and erase operations. Actually, a possible number of time of the write and erase operations associated with the metal-nitride-oxide-semiconductor transistor is 10 to 10.sup.2 times as large as the floating gate transistor since the principal in write erasing operations of the metal-nitride-oxide-semiconductor transistor is completely different from that of the floating gate transistor. It has been known that the above silicon nitride film may be replaced by an aluminium oxide film.
Such metal-nitride-oxide-semiconductor transistors are disclosed, for example, in July 1969 Journal of Applied Physics, Vol. 40, No. 8, pp. 3307-3319 and in November 1974, The Bell System Technical Journal, pp. 1722-1739. A typical metal-nitride-oxide-semiconductor structure is as illustrated in FIG. 1 of the above initial publication and comprises laminations of four layers, namely a semiconductor substrate, a silicon dioxide film formed on the semiconductor substrate, a silicon nitride film formed on the silicon dioxide film and an aluminium gate formed on the silicon nitride film.
The write and erasing operations of the metal-nitride-oxide-semiconductor memory device will hereinafter be described. In the write operation, a positive voltage is applied to the gate electrode so that an electric field is applied across the above four layer laminations to cause hot electrons on a surface region of the semiconductor substrate. The hot electrons may show either a Fowler-Nordheim tunneling or a direct tunneling across the silicon dioxide film and then trapped into interfacial energy states serving as trap center on an interface between the silicon dioxide film and the silicon nitride film. During application of zero voltage to the gate, the trapped electrons incline to be accumulated on the interface of the silicon dioxide and silicon nitride films. This represents "1" in logic states and the write operation was completed.
In the erasing operation, a negative voltage is applied to the gate so that the electrons accumulated on the interface between the above two films may show a reverse direction Fowler-Nordheim tunneling or a reverse direction direct tunneling across the silicon dioxide film into the semiconductor substrate thereby the electrons have emitted from the interface between the above oxide and nitride films. This represents "0" in the logic states and the erasing operation was completed.
It may depend upon a thickness of the silicon dioxide film whether the Fowler-Nordheim tunneling or the direct tunneling appears. If the thickness of the silicon dioxide film is larger than 50 angstroms, the Fowler-Nordheim tunneling appears. By contrast, if the thickness of the silicon dioxide film is smaller than 50 angstroms preferably smaller than 30 angstroms, the direct tunneling appears.
The majority of electrons appears to reside on or near to the interface between the two dielectric layers, or the silicon dioxide film and the silicon nitride film. Notwithstanding, the minority of the electrons appears to penetrate into the silicon nitride film by hopping along the bulk traps. It is hard to emit, in the erasing operation by applying an available electric field, electrons having once penetrated into the silicon nitride film. By contrast, it is relatively easy to emit electrons trapped in the interfacial traps on the interface between the silicon dioxide and silicon nitride films.
The existence, after the erase operation, of electrons in the silicon nitride film may cause an unnecessary electric field under which energy band profiles with respect to the metal-nitride-oxide-semiconductor layers are slightly deformed. Needless to say, such unnecessary electric field caused by the electrons existing in the silicon nitride film is left after the erasure operation. In a subsequent write operation, fresh electrons are further captured in the interfacial traps on the interface between the silicon oxide and nitride films to be accumulated therein for signal storage. Even when no voltage is applied to the gate for a long-time storage, such the unnecessary electric field caused by the electrons having existed in the silicon nitride film after the previous erasing operation may, however, allow some electrons to be emitted from the interfacial traps through the reverse direction tunneling process with a low probability. Namely, the electrons trapped in the interfacial traps may show gradual emission through the reverse direction tunneling across the silicon oxide film. This means that a considerable amount of electrons may be emitted from the interfacial traps for such a very long time as required, for example, 10.sup.5 hours. This renders it hard to trap the informational electrons on the interface between the silicon oxide and nitride films or to achieve a long time storage of informations.
It depends upon a thickness of the silicon dioxide film whether it is easy to prevent electrons trapped in the interfacial traps from being emitted therefrom via the reverse direction tunneling process during no voltage application to the gate for the memory storage. Needless to say, a larger thickness of the silicon dioxide film is preferable in order to secure a prevention of the electrons from any emission. Such large thickness of the silicon dioxide film may, however, act as a bar to the write and erasing operations so as to reduce a probability of the tunneling across the silicon dioxide film under a certain electric field applied. This accords to the principal that increase of a potential barrier width results in a reduction of a probability of tunneling of carriers across the potential barrier under a given electric field. A probability of Fowler-Nordheim tunneling which appears across the thick insulation film is lower than a direct tunneling. inclines appearing across the thin insulation film. When considering each of the Fowler-Nordheim tunneling or the direct tunneling separately, the increase of the width of the insulator or dielectric film results in a reduction of the probability of the each tunneling process.
The reduction of the probability of the tunneling of electrons across the silicon dioxide film may further provide a reduction of a performance speed or result in an increase in time for write and erase operations.
The necessary increase of a low probability of tunneling for realizing the available memory device requires higher voltage applications for the write and erase operations. Such higher voltage applications are undesirable in view of a large power consumption. The thick silicon dioxide film may therefore provide the problem as described above.
By contrast, the use of a thin silicon dioxide film may be free from the above problem with the large voltage applications and the large power consumption. This is, however, engaged with the other problem with difficulty in securing such a long time memory storage as required, for example, 10.sup.5 hours as described above.
There has been known in the art another conventional memory device modified from the above metal-nitride-oxide-semiconductor memory device. The another conventional memory device has three dielectric films between the channel region and the gate electrode so that electrons may be accumulated in an intermediate dielectric film among the three films. This conventional device is disclosed in the Japanese Patent Publication No. 62-33753, a structure thereof is illustrated in FIG. 1, referring to which this device will be described.
Field oxide films 102 are formed on a main face of a silicon substrate 101 to define an active region for transistor. Source and drain regions are formed by impurity diffusions to define a channel region on which the following three dielectric films acting as gate insulators are formed. A bottom silicon oxide film 105 having a thickness of 2.5 to 5 nanometers is formed on the channel region by a thermal oxidation of silicon. An intermediate film 106a made of either silicon nitride or aluminium oxide containing metal atoms such as tungsten is formed on the bottom film 105. The intermediate film has a thickness of 1 to 5 nanometers. A top film 106 made of either silicon nitride or aluminium oxide and having a thickness of 35 to 70 nanometers is formed on the intermediate film 106a. A gate electrode 107 is formed on the top film 106. The gate electrode may comprise a polysilicon film doped with an n-type dopant or an aluminium film. An inter-layer insulator 108 is formed on an entire of the processed surface of the device for subsequent formations of contact holes over the source and drain regions respectively. Source and drain electrodes 109 and 110 are formed to contact to the source and drain regions respectively through the contact holes.
In the write operation, a positive voltage is applied to the gate electrode 107 to cause electrons on the channel region to show a tunneling through the bottom silicon oxide film 105 into the intermediate film 106a in which the electrons having tunneled are accumulated.
In the erase operation, either a negative voltage is applied to the gate electrode 107 or a positive voltage is applied to the silicon substrate 101 to cause the electrons accumulated in the intermediate film 106a to tunnel through the bottom silicon oxide film 105 into the channel region of the silicon substrate 101 for emission of the electrons.
The above conventional device as illustrated in FIG. 1 has the following different feature than the normal two layered gate insulator metal-nitride-oxide-semiconductor memory devices as described above. The gate insulator includes the intermediate film 106a into which electrons are accumulated for memory storage. The intermediate film 106a may contain metal atoms or metal particles uniformly distributed, which may serve as trap centers for electrons. Namely, the intermediate film 106a has a large number of center traps uniformly distributed, for which reason almost all electrons are trapped thereinto. This may present electrons from penetrating into the top film 106, although it is hard to emit the electrons having once penetrated into the top film 106.
As described above, in the normal metal-nitride-oxide-semiconductor memory device, the majority of electrons are trapped into the interfacial trap centers on the interface between the oxide and nitride films, while the minority of electrons incline to penetrate into the nitride film. It is hard to emit the electrons having once penetrated into the nitride film.
The intermediate film 106a having a large number of center traps into which electrons may readily trapped prevents any accumulation of electrons in the top nitride or aluminium oxide film. This may facilitate the erasure operation. The necessary time for either write or erasing operation is reduced to approximately 1 microseconds. The write and erasing operations comes into 10 to 10.sup.4 times as fast as the above normal devices.
The bottom oxide film having the thickness of 2.5 nanometer or more may allow a long time memory storage or may prevent electron emission via electron tunneling through the bottom silicon oxide film into the silicon substrate 101. A possible time for the memory storages comes into 10.sup.5 hours which is 10 to 10.sup.3 times as longer as the normal device.
This conventional memory device illustrated in FIG. 1, however, has two serious problems, one of which is concerned with a high voltage application and another is concerned with a pollution of semiconductor by metal atoms.
The conventional device of FIG. 1 requires a highly voltage application more than 30 V for write and erase operations. This voltage level is considerably higher than voltages 5 V and 12 V as required by the floating gate memory transistor. However, the above normal metal-nitride-oxide-semiconductor memory device also needs such high voltage application as 30 V. In consideration of a hard and earnest requirement for a possible reduction of the voltage to be applied to the gate or for a possible reduction of the power consumption, such a high voltage as approximately 30 V should be reduced considerably at least into 5 V or less.
As described above, the intermediate film 106 has a large number of metal atoms or metal particles acting as the traps for electrons. Such metal atoms or metal particles are mixed into the intermediate film 106a. This may provide a certain possibility of pollution by metal to the silicon substrate. This may results in considerable deteriorations of device performances or device qualities.
From the foregoing descriptions, it may be understood that there has not been any non-volatile memory device free from any problems as described above and a development of such desirable memory device has acutely been required for realizing larger capacity non-volatile memory cells.